This invention relates generally to computer memory, and more particularly to providing performance monitoring in a memory system.
Contemporary high performance computing main memory systems are generally composed of one or more dynamic random access memory (DRAM) devices, which are connected to one or more processors via one or more memory control elements. Overall computer system performance is affected by each of the key elements of the computer structure, including the performance/structure of the processor(s), any memory cache(s), the input/output (I/O) subsystem(s), the efficiency of the memory control function(s), the main memory device(s), and the type and structure of the memory interconnect interface(s).
Extensive research and development efforts are invested by the industry, on an ongoing basis, to create improved and/or innovative solutions to maximizing overall system performance and density by improving the memory system/subsystem design and/or structure. High-availability systems present further challenges as related to overall system reliability due to customer expectations that new computer systems will markedly surpass existing systems in regard to mean-time-between-failure (MTBF), in addition to offering additional functions, increased performance, increased storage, lower operating costs, etc. Other frequent customer requirements further exacerbate the memory system design challenges, and include such items as ease of upgrade and reduced system environmental impact (such as space, power and cooling).
FIG. 1 relates to U.S. Pat. No. 5,513,135 to Dell et al., of common assignment herewith, and depicts an early synchronous memory module. The memory module depicted in FIG. 1 is a dual in-line memory module (DIMM). This module is composed of synchronous DRAMs 8, buffer devices 12, an optimized pinout, and an interconnect and capacitive decoupling method to facilitate high performance operation. The patent also describes the use of clock re-drive on the module, using such devices as phase-locked loops (PLLs).
FIG. 2 relates to U.S. Pat. No. 6,173,382 to Dell et al., of common assignment herewith, and depicts a computer system 10 which includes a synchronous memory module 20 that is directly (i.e. point-to-point) connected to a memory controller 14 via a bus 40, and which further includes logic circuitry 24 (such as an application specific integrated circuit, or “ASIC”) that buffers, registers or otherwise acts on the address, data and control information that is received from the memory controller 14. The memory module 20 can be programmed to operate in a plurality of selectable or programmable modes by way of an independent bus, such as an inter-integrated circuit (I2C) control bus 34, either as part of the memory initialization process or during normal operation. When utilized in applications requiring more than a single memory module connected directly to a memory controller, the patent notes that the resulting stubs can be minimized through the use of field-effect transistor (FET) switches to electrically disconnect modules from the bus.
Relative to U.S. Pat. Nos. 5,513,135, 6,173,382 further demonstrates the capability of integrating all of the defined functions (address, command, data, presence detect, etc) into a single device. The integration of functions is a common industry practice that is enabled by technology improvements and, in this case, enables additional module density and/or functionality.
FIG. 3, from U.S. Pat. No. 6,510,100 to Grundon et al., of common assignment herewith, depicts a simplified diagram and description of a memory system 10 that includes up to four registered DIMMs 40 on a traditional multi-drop stub bus. The subsystem includes a memory controller 20, an external clock buffer 30, registered DIMMs 40, an address bus 50, a control bus 60 and a data bus 70 with terminators 95 on the address bus 50 and the data bus 70. Although only a single memory channel is shown in FIG. 3, systems produced with these modules often included more than one discrete memory channel from the memory controller, with each of the memory channels operated singly (when a single channel was populated with modules) or in parallel (when two or more channels where populated with modules) to achieve the desired system functionality and/or performance.
FIG. 4, from U.S. Pat. No. 6,587,912 to Bonella et al., depicts a synchronous memory module 210 and system structure in which the repeater hubs 320 include local re-drive of the address, command and data to the local memory devices 301 and 302 via buses 321 and 322; generation of a local clock (as described in other figures and the patent text); and the re-driving of the appropriate memory interface signals to the next module or component in the system via bus 300.
FIG. 5 depicts a contemporary system composed of an integrated processor chip 500, which contains one or more processor elements and an integrated memory controller 510. In the configuration depicted in FIG. 5, multiple independent cascade interconnected memory busses 506 are logically aggregated together to operate in unison to support a single independent access request at a higher bandwidth with data and error detection/correction information distributed or “striped” across the parallel busses and associated devices. The memory controller 510 attaches to four narrow/high speed point-to-point memory busses 506, with each bus 506 connecting one of the several unique memory controller interface channels to a cascade interconnected memory subsystem 503 (or memory module) which includes at least a hub device 504 and one or more memory devices 509. Some systems further enable operations when a subset of the memory busses 506 are populated with memory subsystems 503. In this case, the one or more populated memory busses 508 may operate in unison to support a single access request.
FIG. 6 depicts a block diagram of a memory hub device 504 including a link interface 604 for providing the means to re-synchronize, translate and re-drive high speed memory access information to associated DRAM devices 509 and/or to re-drive the information downstream on memory bus 506 as applicable based on the memory system protocol. The information is received by the link interface 604 from an upstream memory hub device 504 or from a memory controller 510 (directly or via an upstream memory hub device 504) via the memory bus 506. The memory device data interface 615 manages the technology-specific data interface with the memory devices 509 and controls the bi-directional memory device data bus 608. The memory hub control 613 responds to access request packets by responsively driving the memory device 509 technology-specific address and control bus 614 (for memory devices in RANK0 501) or address and control bus 614′ (for memory devices in RANK1 616) and directing the read data flow 607 and write data flow 610 selectors.
The link interface 604 in FIG. 6 decodes the packets and directs the address and command information directed to the local hub device 504 to the memory hub control 613. Memory write data from the link interface 604 can be temporarily stored in the write data queue 611 or directly driven to the memory devices 509 via the write data flow selector 610 and internal bus 612, and then sent via internal bus 609 and memory device data interface 615 to memory device data bus 608. Memory read data from memory device(s) 509 can be queued in the read data queue 606 or directly transferred to the link interface 604 via internal bus 605 and read data selector 607, to be transmitted on the upstream bus 506 as a read reply packet.
In high bandwidth cascaded memory architectures, it is highly desirable to measure memory parameters such as channel bandwidth under no load and heavy load conditions to make sure that the interface is being optimally utilized and to validate system performance predictions. Historically, it is the job of the performance and test teams to make sure that the system is configured and being used optimally. A performance benchmark can be executed to measure different memory latency and performance characteristics, but much of the behavior of the interface would have to be inferred from the runtimes of various tests. There is a need to validate the memory interface during runtime (under application conditions) and monitor the multiple interfaces of the whole system to understand where bottlenecks in the system may be occurring. It would be desirable to be able to use these results to program optimized register settings in the current system and/or to modify the design and modify future designs/systems to eliminate those bottlenecks.